A new common-mode voltage reduction technique for multilevel inverters
Ghoreishy, Hoda , Zare, Firuz, Hassanpour, Hamid, & Ledwich, Gerard F. (2007) A new common-mode voltage reduction technique for multilevel inverters. In Australasian Universities Power Engineering Conference, 2007 (AUPEC 2007), 9-12 December, 2007, Perth, Western Australia.
In this paper, a novel common-mode voltage reduction technique is proposed for a three-phase multilevel inverter. The technique can be used to control capacitors voltages and load currents with low switching losses. It can be applied to a three-phase three-level inverter with the flying capacitor topology. One of the advantages of this method is that the technique can be applied to more voltage levels without significantly changing the control algorithm. The simulation results of a five-level inverter in this paper indicate that the proposed technique can be used to implement a multilevel inverter.
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|Item Type:||Conference Paper|
|Keywords:||capacitors, invertors, network topology, switching convertors|
|Subjects:||Australian and New Zealand Standard Research Classification > ENGINEERING (090000) > ELECTRICAL AND ELECTRONIC ENGINEERING (090600)|
|Divisions:||Past > QUT Faculties & Divisions > Faculty of Built Environment and Engineering|
|Copyright Owner:||Copyright 2007 IEEE|
|Copyright Statement:||Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Deposited On:||05 Aug 2008|
|Last Modified:||29 Feb 2012 23:34|
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