Asymmetrical DC link voltage configuration for a diode-clamped inverter
Nami , Alireza, Zare, Firuz, & Ghosh, Arindam (2010) Asymmetrical DC link voltage configuration for a diode-clamped inverter. IEEJ Transactions on Industry Applications (Denki Gakkai Ronbunshi. D, Sangyo Oyo Bumonshi), 130(2), pp. 195-206.
There is a trade off between a number of output voltage levels and the reliability and efficiency of a multilevel converter. A new configuration of diode-clamped multilevel inverters with a different combination of DC link capacitors voltage has been proposed in this paper. Two different symmetrical and asymmetrical unequal arrangements for a four-level diode-clamped inverter have been compared, in order to find an optimum arrangement with lower switching losses and optimised output voltage quality. The simulation and hardware results for a four-level inverter show that the asymmetrical configuration can obtain more output voltage levels with the same number of components compared with a conventional four-level inverter and this will lead to the reduction of the harmonic content of the output voltage. A new family of multi-output DC-DC converters with a simple control strategy has been utilised as a front-end converter to supply the DC link capacitor voltages for the optimised configuration.
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|Item Type:||Journal Article|
|Keywords:||Diode-clmaped converter, Asymmetrical DC link, Adjacent vectors|
|Subjects:||Australian and New Zealand Standard Research Classification > ENGINEERING (090000) > ELECTRICAL AND ELECTRONIC ENGINEERING (090600) > Industrial Electronics (090603)|
|Divisions:||Past > QUT Faculties & Divisions > Faculty of Built Environment and Engineering|
Past > Schools > School of Engineering Systems
|Copyright Owner:||Copyright 2010 The Institute of Electrical Engineers of Japan|
|Deposited On:||08 Mar 2010 10:31|
|Last Modified:||08 Mar 2010 10:31|
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