Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs

Lee, Justin A. & Sitte, Joaquin (2006) Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs. In Stoica, Adrian, Arslan, Tughrul, Suess, Martin, Yalcin, Senay, Keymeulen, Didier, Higuchi, Tetsuya, et al. (Eds.) 1st NASA/ESA Conference on Adaptive Hardware and Systems, 15-18 June 2006, Istanbul, Turkey.

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Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing circuit and FPGA complexity. To overcome this there have been moves towards encoding a growth process, known as morphogenesis, however existing approaches have tended to abstract away the underlying FPGA architecture.

Although currently commercially available FPGAs are not the most evolution-friendly platforms, having complex architectures and issues with potentially damaging configurations, evolving circuits on commercially available devices without requiring a move to high-level building blocks is a necessary prerequisite for the adoption of EHW to solving real problems in electronic design, repair and adaptation.

In this paper we present a morphogenetic EHW model where growth is directed by the gate-level state of the FPGA. We demonstrate that this approach consistently outperforms a traditional EHW approach using a direct encoding, in the number of generations required to find an optimal solution, and in its ability to scale to increases in circuit size and complexity.

Issues in EHW problem solvability are also identified, and preliminary work is presented showing that a morphogenetic approach to EHW may be well suited to correcting damaged circuits.

Impact and interest:

6 citations in Scopus
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ID Code: 4609
Item Type: Conference Paper
Refereed: Yes
Keywords: Evolvable Hardware, Morphogenesis, Adaptive Hardware
DOI: 10.1109/AHS.2006.45
Subjects: Australian and New Zealand Standard Research Classification > ENGINEERING (090000) > ELECTRICAL AND ELECTRONIC ENGINEERING (090600) > Electrical and Electronic Engineering not elsewhere classified (090699)
Australian and New Zealand Standard Research Classification > INFORMATION AND COMPUTING SCIENCES (080000) > ARTIFICIAL INTELLIGENCE AND IMAGE PROCESSING (080100) > Neural Evolutionary and Fuzzy Computation (080108)
Australian and New Zealand Standard Research Classification > TECHNOLOGY (100000) > COMPUTER HARDWARE (100600) > Computer Hardware not elsewhere classified (100699)
Divisions: Past > QUT Faculties & Divisions > Faculty of Science and Technology
Copyright Owner: Copyright 2006 IEEE
Copyright Statement: Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Deposited On: 28 Jun 2006 00:00
Last Modified: 29 Feb 2012 13:28

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