Gate-level Morphogenetic Evolvable Hardware for Scalability and Adaptation on FPGAs

Abstract

Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing circuit and FPGA complexity. To overcome this there have been moves towards encoding a growth process, known as morphogenesis, however existing approaches have tended to abstract away the underlying FPGA architecture.

Although currently commercially available FPGAs are not the most evolution-friendly platforms, having complex architectures and issues with potentially damaging configurations, evolving circuits on commercially available devices without requiring a move to high-level building blocks is a necessary prerequisite for the adoption of EHW to solving real problems in electronic design, repair and adaptation.

In this paper we present a morphogenetic EHW model where growth is directed by the gate-level state of the FPGA. We demonstrate that this approach consistently outperforms a traditional EHW approach using a direct encoding, in the number of generations required to find an optimal solution, and in its ability to scale to increases in circuit size and complexity.

Issues in EHW problem solvability are also identified, and preliminary work is presented showing that a morphogenetic approach to EHW may be well suited to correcting damaged circuits.