A Single-Bit Digital DC-Blocker Using Ternary Filtering
In this paper, a single-bit dc-blocker is presented. It is comprised of a ternary ifitering stage preceded by a sigma-delta modulator. Different techniques are used to generate the ternary taps for hardnare and performance optimization. Both the input and the output of this dc-blocker are assumed in single-bit format. The proposed dc-blocker can easily be implemented with FPGA.
Impact and interest:
Citation counts are sourced monthly from and citation databases.
Citations counts from theindexing service can be viewed at the linked Google Scholar™ search.
Full-text downloads displays the total number of times this work’s files (e.g., a PDF) have been downloaded from QUT ePrints as well as the number of downloads in the previous 365 days. The count includes downloads for all files if a work has more than one.
|Item Type:||Conference Paper|
|Subjects:||Australian and New Zealand Standard Research Classification > ENGINEERING (090000) > ELECTRICAL AND ELECTRONIC ENGINEERING (090600) > Signal Processing (090609)|
|Divisions:||Past > QUT Faculties & Divisions > Faculty of Built Environment and Engineering|
|Copyright Owner:||Copyright 2005 IEEE|
|Copyright Statement:||Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Deposited On:||02 Jan 2007 00:00|
|Last Modified:||29 Feb 2012 13:11|
Repository Staff Only: item control page