Studies in power hardware in the loop (PHIL) simulation using real-time digital simulator (RTDS)
Dargahi, Mahdi, Ghosh, Arindam, Ledwich, Gerard, & Zare, Firuz (2012) Studies in power hardware in the loop (PHIL) simulation using real-time digital simulator (RTDS). In Proceedings of the 2012 IEEE International Conference on Power Electronics, Drives and Energy Systems, IEEE, Bengaluru, India, pp. 1-6.
In power hardware in the loop (PHIL) simulations, a real-time simulated power system is interfaced to a piece of hardware, usually called hardware under test (HuT). A PHIL test can be realized using several simulation tools. Among them Real Time Digital Simulator (RTDS) is an ideal tool to perform complex power system simulations in near real-time. Stable operation of the entire system, along with the accuracy of simulation results are the main concerns regarding a PHIL simulation. In this paper, a simulated power network on RTDS will be interfaced to HuT through a voltage source converter (VSC). Issues around stability and other interface problems are studied and a new method to stabilize some unstable PHIL cases is proposed. PHIL simulation results in PSCAD and RSCAD are presented.
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|Item Type:||Conference Paper|
|Keywords:||Power hardware in the loop, RTDS, Interface algorithms, Stability of PHIL|
|Divisions:||Current > Schools > School of Earth, Environmental & Biological Sciences
Current > Schools > School of Electrical Engineering & Computer Science
Current > QUT Faculties and Divisions > Science & Engineering Faculty
|Copyright Owner:||Copyright 2012 IEEE|
|Deposited On:||26 Apr 2013 01:05|
|Last Modified:||12 Jun 2013 15:43|
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