Performance evaluation of three-level Z-source inverters under semiconductor-failure conditions
Gao, Feng, Loh, Poh Chiang, Blaabjerg, Frede, & Vilathgamuwa, D. Mahinda (2009) Performance evaluation of three-level Z-source inverters under semiconductor-failure conditions. IEEE Transactions on Industry Applications, 45(3), pp. 971-981.
This paper evaluates and proposes various compensation methods for three-level Z-source inverters under semiconductor-failure conditions. Unlike the fault-tolerant techniques used in traditional three-level inverters, where either an extra phase-leg or collective switching states are used, the proposed methods for three-level Z-source inverters simply reconfigure their relevant gating signals so as to ride-through the failed semiconductor conditions smoothly without any significant decrease in their ac-output quality and amplitude. These features are partly attributed to the inherent boost characteristics of a Z-source inverter, in addition to its usual voltage-buck operation. By focusing on specific types of three-level Z-source inverters, it can also be shown that, for the dual Z-source inverters, a unique feature accompanying it is its extra ability to force common-mode voltage to zero even under semiconductor-failure conditions. For verifying these described performance features, PLECS simulation and experimental testing were performed with some results captured and shown in a later section for visual confirmation.
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|Item Type:||Journal Article|
|Keywords:||Fault compensation, Three-level inverter, Z-source inverter|
|Divisions:||Current > Schools > School of Electrical Engineering & Computer Science
Current > QUT Faculties and Divisions > Science & Engineering Faculty
|Copyright Owner:||Copyright 2009 IEEE|
|Deposited On:||21 Jul 2014 22:48|
|Last Modified:||22 Jul 2014 22:51|
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