Stability synthesis of power hardware-in-the-loop (PHIL) simulation

Dargahi, M., Ghosh, A., & Ledwich, G. (2014) Stability synthesis of power hardware-in-the-loop (PHIL) simulation. In Proceedings of the 2014 IEEE PES General Meeting | Conference & Exposition, IEEE, National Harbor, MD, pp. 1-5.

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Abstract

A virtual power system can be interfaced with a physical system to form a power hardware-in-the-loop (PHIL) simulation. In this scheme, the virtual system can be simulated in a fast parallel processor to provide near real-time outputs, which then can be interfaced to a physical hardware that is called the hardware under test (HuT). Stable operation of the entire system, while maintaining acceptable accuracy, is the main challenge of a PHIL simulation. In this paper, after an extended stability analysis for voltage and current type interfaces, some guidelines are provided to have a stable PHIL simulation. The presented analysis have been evaluated by performing several experimental tests using a Real Time Digital Simulator (RTDS™) and a voltage source converter (VSC). The practical test results are consistent with the proposed analysis.

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ID Code: 80158
Item Type: Conference Paper
Refereed: Yes
Keywords: PHIL, RTDS, Real-time simulation, Interface issues, Stability of PHIL
DOI: 10.1109/PESGM.2014.6939021
ISBN: 9781479964154
Divisions: Current > Schools > School of Electrical Engineering & Computer Science
Current > QUT Faculties and Divisions > Science & Engineering Faculty
Copyright Owner: Copyright 2014 by IEEE
Deposited On: 15 Jan 2015 23:51
Last Modified: 19 Jan 2015 20:50

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