Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI
Sievers, Gregor, Ax, Johannes, Kucza, Nils, Flasskamp, Martin, Jungeblut, Thorsten, Kelly, Wayne A., Porrmann, Mario, & Rückert, Ulrich (2015) Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI. In Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, Cultural Centre of Belém, Lisbon, pp. 1925-1928.
Embedded many-core architectures contain dozens to hundreds of CPU cores that are connected via a highly scalable NoC interconnect. Our Multiprocessor-System-on-Chip CoreVAMPSoC combines the advantages of tightly coupled bus-based communication with the scalability of NoC approaches by adding a CPU cluster as an additional level of hierarchy. In this work, we analyze different cluster interconnect implementations with 8 to 32 CPUs and compare them in terms of resource requirements and performance to hierarchical NoCs approaches. Using 28nm FD-SOI technology the area requirement for 32 CPUs and AXI crossbar is 5.59mm2 including 23.61% for the interconnect at a clock frequency of 830 MHz. In comparison, a hierarchical MPSoC with 4 CPU cluster and 8 CPUs in each cluster requires only 4.83mm2 including 11.61% for the interconnect. To evaluate the performance, we use a compiler for streaming applications to map programs to the different MPSoC configurations. We use this approach for a design-space exploration to find the most efficient architecture and partitioning for an application.
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|Item Type:||Conference Paper|
|Divisions:||Current > Schools > School of Electrical Engineering & Computer Science
Current > QUT Faculties and Divisions > Science & Engineering Faculty
|Copyright Owner:||Copyright 2015 [Please consult the author]|
|Deposited On:||21 Jun 2015 23:03|
|Last Modified:||12 Sep 2015 16:17|
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