System-level analysis of network interfaces for hierarchical MPSoCs
Ax, Johannes, Sievers, Gregor, Flasskamp, Martin, Kelly, Wayne, Jungeblut, Thorsten, & Porrmann, Mario (2015) System-level analysis of network interfaces for hierarchical MPSoCs. In Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc), ACM, Waikiki, Hawaii, pp. 3-8.
Network Interfaces (NIs) are used in Multiprocessor System-on-Chips (MPSoCs) to connect CPUs to a packet switched Network-on-Chip. In this work we introduce a new NI architecture for our hierarchical CoreVA-MPSoC. The CoreVA-MPSoC targets streaming applications in embedded systems. The main contribution of this paper is a system-level analysis of different NI configurations, considering both software and hardware costs for NoC communication. Different configurations of the NI are compared using a benchmark suite of 10 streaming applications. The best performing NI configuration shows an average speedup of 20 for a CoreVA-MPSoC with 32 CPUs compared to a single CPU. Furthermore, we present physical implementation results using a 28 nm FD-SOI standard cell technology. A hierarchical MPSoC with 8 CPU clusters and 4 CPUs in each cluster running at 800MHz requires an area of 4.56mm2.
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|Item Type:||Conference Paper|
|Keywords:||B.4.3 [Interconnections (Subsystems)]: Interfaces;, C.1.4 [Parallel Architectures]|
|Subjects:||Australian and New Zealand Standard Research Classification > INFORMATION AND COMPUTING SCIENCES (080000) > COMPUTER SOFTWARE (080300) > Concurrent Programming (080304)|
|Divisions:||Current > Schools > School of Electrical Engineering & Computer Science
Current > QUT Faculties and Divisions > Science & Engineering Faculty
|Copyright Owner:||Copyright 2015 The Author(s)|
|Deposited On:||19 Apr 2016 23:47|
|Last Modified:||24 Apr 2016 05:40|
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