A Single-Bit Digital DC-Blocker Using Ternary Filtering

Sadik, Amin Z. and Hussain, Zahir M. and O'Shea, Peter J. (2005) A Single-Bit Digital DC-Blocker Using Ternary Filtering . In Proceedings IEEE Tencon '05, Melbourne.

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Abstract

In this paper, a single-bit dc-blocker is presented. It is comprised of a ternary ifitering stage preceded by a sigma-delta modulator. Different techniques are used to generate the ternary taps for hardnare and performance optimization. Both the input and the output of this dc-blocker are assumed in single-bit format. The proposed dc-blocker can easily be implemented with FPGA.

Item Type:	Conference Paper
Status:	Published
Subjects:	280000 Information, Computing and Communication Sciences > 280200 Artificial Intelligence and Signal and Image Processing > 280204 Signal Processing
ID Code:	5914
Deposited By:	Mason, Bonnie
Deposited On:	02 January 2007
Alternative Locations:	http://dx.doi.org/10.1109/TENCON.2005.301222
Copyright Owner:	Copyright 2005 IEEE
Copyright Statement:	Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.