SiC-Based Active Quasi-Z-Source Inverter with Improved PWM Control Strategy

: In this paper, an improved PWM scheme is proposed for an active quasi-Z source inverter (AqZSI). Compared to the quasi-Z-source inverter (qZSI), the AqZSI with improved PWM strategy can operate in a wide range of input voltage with a higher efficiency. Furthermore, the AqZSI can operate with a higher modulation index, a lower inductor current stress, and a reduced shoot-through current. A procedure flowchart is presented for the optimal selection of the shoot-through duty cycle, the switching ratio of the additional switch, and the modulation index for AqZSI. Moreover, some comparative results between the AqZSI, qZSI and conventional two-stage inverter with a boost DC-DC converter are shown in detail. Finally, 1.2-kVA SiC-based three-phase inverter prototypes are built to verify the agreement between theory and measurement.


Introduction
The renewable energy sources such as photovoltaics (PVs), wind power, and fuel cell stacks are found to be attractive solutions in global efforts of making power generation environmentally friendly. Micro-grids and small scale distribution systems, comprised of distributed power, energy sources, energy conversion devices, energy storage devices, local loads, and protection devices play an essential role in distributed power generation. For interfacing renewable energy sources to distributed power grid, power inverters play an important role [1]. Voltage source inverters (VSIs) are the most established DC-AC power converter in any electric power system. However, VSIs can only handle a buck conversion where the DC bus input voltage is always higher than that of the output AC voltage. In order to improve the boost capability of the traditional VSI, the two-stage boost converter based VSI (BC-VSI) [2]- [3] is implemented by adding a boost DC-DC converter between the energy source and the conventional H-bridge inverter. In the BC-VSI, the short-circuiting of the DC-link bus in the inverter stage is prevented, and a dead-time must be inserted into the switching pulses of each phase leg switches owing to the limited switching transition times of the switches. Some compensating techniques are proposed in [4]- [5] to evaluate the dead-time effect and as a consequence the complexity of the VSI control system is increased.
Recently, to overcome the aforementioned limitations in two-stage BC-VSI power conversion systems, studies on single-stage power conversion have been conducted intensely. Z-source and quasi Z-source inverters (ZSI/qZSIs) presented in [6]- [9] belong to a family of first types of such single-stage power conversion systems. They can be used for power conversion from the low voltage sources to any desired AC voltage without the shoot-through (ST) problem theoretically. In practice, however, the voltage gain of ZSI/qZSIs is limited by the parasitic elements of the topology. Some comparisons between single-stage qZSIs and conventional two-stage inverters are given in [10]- [13]. In [10], a comparison between BC-VSI and ZSI for fuel-cell vehicles is presented.
In this comparison, it is shown that in cases where power switches with high switching loss are used for high power applications, ZSI is very competitive with great reliability and higher efficiency when the boost ratio is lower than 2. In the same way, qZSI is compared with BC-VSI in the low voltage gain region of (1 -2) and at a switching frequency of 10 kHz as addressed in [11]. qZSI is shown to have a lower THD and higher efficiency than that of the BC-VSI. According to comparison results in [11], the switching frequency of the active switch in boost stage is five times the switching frequency of the H-bridge inverter. Furthermore, a wide band-gap device based BC-VSI and qZSI are discussed in [12]- [13]. The three-phase three-level VSI and qZSI expressed in [12] are tested under identical conditions with a low voltage gain of 1.33 and a switching frequency of 50 kHz. The size of passive components and loss contribution are presented, and it is shown that the qZSI does not have obvious advantages in comparison to BC-VSI under these circumstances. In [13], a SiC-based 6-kW/100-kHz qZSI and BC-VSI prototypes are investigated and comparisons are According to findings of this study, qZSI shows superior THD upto 40 th harmonic but BC-VSI has a better power density.
By considering the number of active switches in the Znetwork, the impedance source inverters can be divided into two main types: passive in [14]- [17] and active in [18]- [23]. The passive qZSIs depicted in Fig. 1(a) show a good performance in low boost voltage applications. When high boost voltages are required, a large ST duty cycle needs to be applied to qZSI. Consequently, qZSI has a high conduction loss because it carries a high ST current that is equal to twice the input current [17]. In order to overcome the limitations of qZSI, a large number of high boost impedance source inverter topologies have been developed by adding active and passive components to the impedance source network. In these structures, the use of a large number of components in the Zsource network may not be appropriate for high power applications because of the increase in power losses and low efficiency.
A family of quasi-switched boost inverters (qSBIs) is proposed in [24] with reduced number of passive components. As introduced in [25], qSBI can be used to replace qZSI when the voltage gain of 2 to 3 is required. Some modified PWM methods for qSBI are introduced to enhance the performance of qSBI. For instance, a new family of n-pulse PWM scheme is proposed in [26] by combining ST mode and turning-on state of the active switch. The n-pulse PWM scheme can improve the modulation index, reduce the input current ripple, and decrease component stresses. However, this PWM technique is more complex, and it increases switching loss of the additional switch in the impedance source network. To achieve the same outcomes, another PWM scheme is proposed for qSBI in [27]. This PWM method shows some advantages; specifically, it can reduce the switching loss of the additional switch. But the ST time interval and turning-on time of the additional switch are interdependent and not selected optimally.
The qSBIs can operate with low ST duty cycles in the modified PWM methods [26] [27]. However, qSBIs have a significant performance deterioration in buck mode of operation when the additional switch is turned off and the inverter operates without ST state. To avoid the unwanted operating states of qSBI at low ST duty cycle, one of the diode in the switched-boost network needs to be replaced by an active switch as presented in [28]. This is not a good solution because two additional switches need to be used in the Z-network and the switches of each phase leg require a dead time.
In order to overcome limitations in qZSI and qSBI, an active qZSI (AqZSI) topology in Fig. 1(b) is proposed in [21]. By adding one more switch and a diode to the Z-source network, AqZSI topology with 3-pulse PWM method is shown to exhibit high voltage gain, low voltage stress on components, and low input current ripple than qZSI [21]. However, the overall performance of AqZSI and comprehensive comparison between AqZSI, qZSI, and BC-VSI are not presented in [21]. This paper presents and evaluates the performance of the single-stage three-phase AqZSI with improved PWM scheme for a wide range of input voltages. In the improved PWM technique, the ST duty cycle and the turning-on state of S0 are independently controlled with a simple PWM generation. By combining the variables of the modulation index, the ST duty cycle, and the duty cycle of the active switch, AqZSI can provide a wider input voltage operating range with higher efficiency. To study and verify the advantage of AqZSI with improved PWM scheme, a comprehensive comparison between the BC-VSI, qZSI, AqZSI with PWM scheme in [21] and AqZSI with improved PWM scheme is presented. 1.2-kVA SiC-based three-phase inverter prototypes are built to evaluate the analysis.
In the next section, the operational considerations of new PWM strategy for AqZSI are introduced. Section 3 discusses the control parameter selection for optimization. The power loss calculation is presented in Section 4. Section 5 compares AqZSI with improved PWM scheme and the BC-VSI, qZSI, and AqZSI with PWM scheme in [21]. Then, the experimental results are described in Section 6. Finally, the conclusions are given in Section 7.

Improved PWM Control Strategy
In this section, the improved PWM scheme is applied for the three-phase AqZSI. Fig. 2 shows the improved PWM method based on the maximum constant boost method with third harmonic injection for the three-phase AqZSI, where the control signal of the additional switch S0 and the ST signal are generated independently. In Fig. 2, D, D0, and T represent ST duty cycle, duty cycle of S0 switch, and switching period, respectively. Three-phase reference voltages va, vb, and vc are Fig. 2. Improved PWM method and key waveforms of AqZSI. compared with the triangle waveform vtr1 to produce the control signal of H-bridge switches. The ST state with the interval time of D·T is created by comparing the reference signal VST and the triangle waveform vtr2. On the other hand, the switch S0 can be turned on during the non-shoot-through (NST) states of the H-bridge circuit with the time interval of D0·T. A constant voltage V0 is compared with vtri2 which has twice the frequency of vtri1 to produce the PWM for the switch S0. The operating states of AqZSI are ST state, NST state 1 and NST state 2 which are comprehensively explained below.

Operating Principles
ST state [ Fig. 3(a), during D·T]: Fig. 3(a) depicts the equivalent circuit of AqZSI in the ST state. Here, only the three-phase H-bridge switches are turned on simultaneously, while S0 is switched off. The diode D1 is reverse-biased, while the diode D2 is forward-biased. In this mode, the inductors L1 and L2 store energy, while the capacitors C1 and C2 are discharged. The following formulas can be written where IPN is the average DC-link current in NST states.

Boost Factor and Voltage Gain
In the steady state, the average voltage across the inductors (L1 and L2) and the average current through the capacitors (C1 and C2) over one switching period are zero. Applying the volt-second balance principle to the inductors and the charge-second balance principle to the capacitors, from (1) to (3), we can obtain the following voltages for capacitors C1 and C2: The peak DC-link voltage in the NST states is The boost factor of AqZSI is rewritten as The peak AC output phase voltage is given by where M is the modulation index and is limited to In one switching period, the average value of the capacitor current is zero. By using the equations (1)-(3), the average current through L1 and L2 inductors can be calculated as follows.
where IPN is defined as the average DC-bus current and is equal to where Rl is the simplified equivalent DC load of the inverter's AC side circuit and is calculated based on the resistive load R as (11).

Analytical Study with Parasitic Components in NST State
The boost factor of AqZSI can be determined by the selection of D and D0 as shown in (6). In addition, M will be calculated at the maximum value of ( ) . To find the optimal values of D and D0, the constrained optimization theory explained in Section 3 will be used. In this optimal solution, the value of D0 must be limited and AqZSI is operated in NST to improve the performance. Hence, the analytical equivalent circuit with parasitic components in NST state is discussed in this subsection. The DC circuit analysis of AqZSI is conducted with the following assumptions: 1) the inverter is operated in continuous conduction mode; 2) the parasitic resistance of the inductors and the equivalent series resistance (ESR) of the capacitors are defined as rL and rC, respectively; 3) the resistance of all switches is rS; 4) the resistance of all diodes is rD; 5) the switching frequency is greater than the frequency of the AC output voltage, and 6) the ST state is disabled (D = 0). The equivalent circuits of AqZSI without ST state are shown in Mode 2 [ Fig. 4 The following equations can be written.
Supposing no losses in the H-bridge inverter, the output power is equal to the power transferred through DClink in the NST states. The output power is defined as In steady state, the average inductor voltage across L1 and Ll over one switching period is zero. From (12) to (14), we have Using (13) The boost factor B of AqZSI versus the duty cycle D0 at D = 0 is shown in Fig. 5. Note that line (1) in Fig. 5 shows the ideal case with rS = rL = rC = rD = 0, whereas lines (2) and (3) indicate the parasitic case with the resistive load R = 35 Ω (full-load) and R = 70 Ω (50% full-load), respectively. The value of parasitic resistance is defined as in the experimental verification as follow: rS = 0.8rL = rC = 1.5rD = 78 mΩ. The boost factor with non-ideal components in lines (2) and (3) reaches its peak and then goes down as the duty cycle D0 is increased to 1. From the plot structure of Fig. 5, it can be seen that the boost factor value of the full-load case is lower than that of the ideal and 50% full-load cases. In this case, we chose the maximum value of D0 based on the full-load operating condition. We can see AqZSI has a near-ideal region with a good performance, has a shallow slope in B-D0 characteristics and easy to control when D0 is from 0 to 0.55. There are obvious differences between ideal and non-ideal line (2)-(3) when D0 is higher than 0.6. Thus, the maximum value of D0 is selected as 0.55.

Design Guideline Optimal Control Parameter Selection
The values of M, D, and D0 are directly related to the voltage gain. Alternatively, the value of D is associated with the duration of ST state in the H-bridge, voltage and current stresses of power components, and the system power losses of AqZSI. In order to improve the value of M and to reduce the power losses, D will be kept as small as possible. Fig. 6 shows the flowchart of the optimal control parameter calculation. As shown in Fig. 6, the input values of the process are the input voltage, Vi and the peak value of ac output voltage, Vo. The calculation value of gain voltage, Gref is defined as 2Vo/Vi. The initial values of M, D, and D0 are set to 1.15, 0 and 0, respectively. In this flowchart, j is the step change which is a very small value. The selection process in the flowchart has two cases as follows Case (i): Gref < 1. 15. As shown in the right branch of Fig. 6, the inverter operates in buck mode with the voltage gain lower than 1x1.15 similar to a conventional VSI. In this case, D and D0 are set to zero. If M happens to be higher than Gref, M will be decreased by step values of j so that M is kept lower or equal to Gref. The loop is completed with D = D0 = 0 and Greal = M.
Case (ii): Gref ≥ 1.15. The inverter is set to operate in boost mode, and D0 is increased with step values of j. In this mode D0 is limited to its maximum value D0_max. If D0 ≤ D0_max, Greal is just dependent on M and D0, and equal to M/(1-D0). Otherwise, D0 is kept to D0_max, and the value of D will be increased by step values of j. In this case, the inverter is operating with the ST state, and the real voltage gain Greal is    Based on the analysis in Section 2.4 with parasitic components of the AqZSI, the maximum value of D0 is selected as 0.55. From (18), the voltage gain curve consists of two parts. The relationships between G and M, duty cycles D0 and D are shown in Fig. 7 where D0_max = 0.55. Fig. 7(a) shows the variation of voltage gain versus M in buck mode. Fig. 7(b) shows the voltage gain versus D0 when D = 0. The value of D0 is changed from 0 to D0_max when the voltage gain is increased from 1.15 to 2.56. Fig. 7(c) shows the voltage gain versus D when D0 = 0.55. In Fig.7(c), the voltage gain is varied in the range of [2.56, +∞) when D is increased from 0 to 0.31.

Power loss in switches
Power loss in switches are predominantly conduction loss and switching loss. The conduction loss of the AqZSI is the conduction loss of switch S0 and H-bridge switches, and is determined as where where fs, ton, toff, and Qrrb are the switching frequency of Hbridge, the turn-on and turn-off delay times of SiC MOSFET switch, and the reverse recovery charge of the body diode, respectively.

Power loss in diodes
The power loss in the diodes comprises of the conduction loss and reverse recovery loss, and is calculated as where uD1, uD2, RD1, RD2, Qrr1 and Qrr2 are the ON-state zerocurrent voltage and the ON-state resistance, reverse recovery charge of the diodes D1 and D2, respectively.

Power loss in capacitors
The power loss in C1 and C2 capacitors is expressed as  AqZSI with improved PWM Boost Factor

Power loss in inductors
The power loss in the inductors comprises of the core loss and the copper loss.
where IL1_rms and IL2_rms are the RMS inductor current through inductors L1 and L2, respectively. The detailed power loss comparison is presented in the next section.

Comparison Criteria for AqZSI, qZSI, and BC-VSI
A comprehensive comparison between AqZSI and the other high voltage gain impedance source inverters was presented in [21]. In this section, a comparison between the proposed PWM scheme and the conventional PWM scheme in [21] for AqZSI, qZSI and BC-VSI is presented. Table 1 shows the key equations of AqZSI with improved PWM scheme, AqZSI with PWM scheme in [21], and qZSI.

Input Current Ripple and Boost Factor
The input current ripple of the BC-VSI is given as where fs is the switching frequency.
In the qZSI, the stored energy of L1 and L2 inductors in the ST state is largest. Thus, the peak to peak current ripples of the inductors L1 and L2 are determined as i L1 By solving (27), the peak-to-peak value of the current ripple for L1 is calculated as The slope of inductor L2 current is the same and equal to -VC2/L2 for both ST state and NST states as presented in Fig. 3. The peak-to-peak inductor L2 current ripple is determined as Substituting the expression of VC1 and VC2 into (30), the peak-to-peak inductor L2 current ripple can be rewritten as  Fig. 9(a) shows the relationship between the input current ripple versus the voltage gain and the boost factor versus shoot-through duty cycle of the inverters when D0_max = 0.55. The inductor current ripple of AqZSI with improved PWM scheme is equal to that of BC-VSI when G ≤ 2.56. The inductor current ripple of AqZSI with improved PWM scheme is lower than that of BC-VSI when G is varied in (2.56, 9.13]. Alternatively, the input current ripple of AqZSI is always lower than that of the qZSI. Moreover, compared to AqZSI with the PWM scheme in [21], AqZSI with improved PWM scheme has a lower input current ripple when G is varied in [5.99, 7.47]. As shown in the right side of Fig. 9(a), the boost factor of AqZSI with improved PWM scheme is highest.
We have the boundary condition of the capacitor C1 voltage ripple as Thus, the selected capacitance of C1 is calculated as The capacitance of C2 can be written as

Voltage and Current Stress
The voltage stress Vs on the H-bridge inverter of BC-VSI is calculated as The voltage stress on the H-bridge inverter of qZSI is calculated The voltage stress on the H-bridge inverter of AqZSI is determined as The ST current and the input current of qZSI and AqZSI are calculated as As shown in (42), the ST current of the AqZSI with improved PWM scheme is lower the qZSI when D0 > 0.
Based on (39)-(41) and Table 1, the voltage and current stress comparison between the BC-VSI, qZSI, AqZSI [21] and AqZSI with improved PWM scheme is shown in Fig.  9(b)-(c). The voltage stress of H-bridge inverter switches in BC-VSI and AqZSI with improved PWM is identical when the voltage gain is lower than M/(1 -D0_max). In contrast, the voltage stress of AqZSI with improved PWM is higher than that of the BC-VSI when the voltage gain is over M/(1 -D0-_max).
AqZSI with improved PWM scheme has a lower voltage stress on H-bridge inverter switches when compared with the qZSI and AqZSI [21]. However, voltage stresses of capacitor C1 and switch S0 of aforementioned inverters are identical but the capacitor C2 voltage of AqZSI with improved PWM scheme is lower than that of the qZSI and AqZSI [21]. Because inductor L1 is directly connected to the DC source, the inductor L1 current stress of the aforementioned inverters is the same. The current stress of inductor L2 and ST current stress of AqZSI with improved PWM scheme are lowest because the ST duty cycle of AqZSI with improved PWM scheme is minimized under optimal control conditions.

Power Loss
In this section, the power loss of the AqZSI with improved PWM scheme will be compared to BC-VSI, qZSI and AqZSI [21]. The power loss calculation is based on that presented in Section 4. Table 2 shows the circuit parameters of the inverters used in the power loss calculation. The SiC semiconductor devices were used to match the experiment. Fig. 10 shows the loss distribution in the inverters at 1037 W output power and the voltage gains of 1.05, 1.5 and 3.19. At a low voltage gain of 1.05 in buck mode, AqZSI with improved PWM method is the same as that in [21]. The diode loss of AqZSI is dominant owing to the full conduction of the additional D2 diode. This leads to high conduction loss in AqZSI. At a voltage gain of 1.5 in boost mode, the switch loss Fig. 10. Loss comparison between BC-VSI, qZSI, AqZSI [21], and AqZSI with improved PWM scheme: (a) G = 1.05, (b) G  = 1.5, and (c of qZSI is highest because the ST state is used in qZSI. In the same way, the power loss of AqZSI [21] is higher than that of AqZSI with improved PWM scheme. This is because the ST state is not applied to AqZSI with improved PWM scheme, while it is used in the PWM scheme in [21]. At the high voltage gain of 3.19, the loss contribution of AqZSI is lower than that of qZSI, AqZSI [21]. This is because the minimal use of ST duty cycle by AqZSI compared to large ST duty cycle used in qZSI, AqZSI [21]. In all three aforementioned cases considered, the loss in BC-VSI is lower than that of qZSI, AqZSI [21], AqZSI with improved PWM scheme.

Dead-Time Effect and Output Quality
The BC-VSI is able to operate at the maximum modulation index of 1x1.15. However, it has a ST problem. In order to avoid the short circuit in the BC-VSI, the deadtime between the upper and lower switches is needed. This leads to a reduction in the output voltage quality of BC-VSI as compared to the other single-stage Z-source inverters.
For the single-stage conversion, qZSI and AqZSI can work in the ST state, and hence, it does not need any deadtime and compensation circuits. When compared to qZSI, AqZSI uses a higher modulation index to generate the same voltage gain. Thus, a better output quality can be found in the AqZSI.

Experiment Results
To perform a comprehensive comparison, 1.2-kVA SiC-based inverter prototypes are built according to the following specifications. In the power circuit, the inverter feeds to a star-connected resistive load through an L-C filter with the values of 1 mH and 10 µF. The input DC voltage range is from 100 V to 350 V. The output phase voltage is 110 Vrms/ 50 Hz. The switching frequency of H-bridge inverter is 30 kHz. Parameters of BC-VSI, qZSI, and AqZSI are shown in Table 3. Furthermore, all switches of BC-VSI, qZSI, and AqZSI are SiC power MOSFETs SCT3060AL (650 V, 39 A, RDSon = 78 mΩ).
For qZSI, the selected Z-source network parameters are L1 = L2 = 1 mH, C1 = 220 μF/400 V and C2 = 220 μF/200 V. The SiC Schottky diodes of IDH16G65C6 are used for D1. In AqZSI, one more SiC MOSFET SCT3060AL and one more SiC Schottky diodes of IDH16G65C6 are added to Zsource network of qZSI. Moreover, the capacitor C2 in AqZSI is changed to 220 μF/100 V. This is because the value of D in AqZSI is decreased by following the flowchart for the modulation index optimization as presented in Section 3. According to (4), the capacitor C2 voltage stress of AqZSI is reduced when D is reduced. Note that the inductance and capacitance selections of AqZSI are considered when AqZSI is operated in the voltage gain of 3.19 and the full-load of 1037 W. To limit the current ripples of L1 and L2 to 10 %, the inductance values of L1 and L2 are selected 1 mH. Also, to limit the voltage ripple of capacitor C1 and C2 to 1%, the capacitances C1 and C2 are selected as 220 μF. In order to ensure AqZSI operates in continuous conduction mode, from (34) and (35), the minimum output power of 145 W is tested.
To confirm the efficiency improvement of AqZSI, the prototype of three-phase BC-VSI is constructed. In the construction of the boost stage of BC-VSI, schottky IDH16G65C6, and a 470 μF/400 V capacitor are used. The dead-time between the two switches on each phase leg is set to 0.4 µs. The values of input and output power of three topologies are obtained from the YOKOGAWA WT230 and HIOKI PW3360 power meter measurements, respectively. In the AqZSI, the values of M, D, and D0 are selected by following the flowchart calculation in Section 3. In BC-VSI, the modulation index M is fixed at its maximum value of 1x1.15. On the other hand, qZSI control parameters are selected by using M = 1.15(1 -D). Fig. 11 shows a photo of the assembled prototypes and experimental setup.

Experimental waveforms of AqZSI with
improved PWM scheme and qZSI Fig. 12 shows the experimental results of qZSI and AqZSI when Vi = 100 V, Vo = 110 Vrms, D = 0.09, M = 1.15×0.913, R = 40 Ω, and Rl = 88 Ω. As shown in Fig. 12(a), the peak-to-peak input ripple current of AqZSI is 1 A lower than that of qZSI of 1.96 A. In the same way, the peak-topeak inductor L2 current ripple of AqZSI of 0.5 A is also lower than that of qZSI. In this case, the dc-link voltage of qZSI is higher than that of AqZSI so that the voltage stress of switches on H-bridge circuit of AqZSI can be reduced. Figs. 12(c) show the experimental waveforms of the output phase current and its harmonics. The measured THD of the output phase current for qZSI and AqZSI are 2.4% and 2.2%, respectively. Compared to qZSI, AqZSI achieves a larger modulation index. Therefore, the output voltage quality of the AqZSI can be improved. In order to verify the AqZSI with improved PWM method, the values of the voltage gain, boost factor, DC-link voltage, capacitors voltage, inductors current and inductors current ripple were measured when the power load changed from 145 W to 1037 W. As shown in Fig. 13, it can be seen that the measured values are slightly changed when the power load is increased. Fig. 5 also shows the experimental boost factor versus the duty cycle D0 to confirm the near ideal region operation of the converter from the analysis in Section 2.4. The values of the boost factor in experiment are measured at Vi = 100 V and full-load of 1037 W when the duty cycle D0 changes from 0 to 0.75. It can be seen from Fig. 5 that the value of parasitic case is matched with experiment case. Fig. 14 shows the experimental results of the AqZSI with improved PWM scheme when the input voltage is 350 V (G = 0.91) and 250 V (G = 1.27). In the buck mode with G = 0.91, the peak DC-link voltage is equal to the capacitor C1 voltage of 350 V while the switch S0 is always turned off. The value of capacitor C2 voltage is about zero, the measured THD of the output phase current is 2.4% as shown in Fig.  14(a). In this case, the inverter operates with turning switch S0 off and without ST state at a modulation index of 0.91. In Fig. 14(b), the inverter operates at a low boost voltage with G = 1.27, maximum modulation index of 1.15 and without ST state. Switch S0 is turned on with D0 = 0.1. It can be seen that the peak DC-link voltage is also equal to the capacitor C1 voltage of 276 V. The measured THD of the output phase  current is 2.3%, while the measured peak-to-peak inductor L1 current is 0.4 A, which is consistent with the calculated value from (28).

Efficiency Comparison
Figs. 15-16 compare the measured efficiency of BC-VSI, qZSI and AqZSI with improved PWM scheme when the output power is varied from 145 W to 1037 W. The voltage gain in the experiment are G = 0.91, G = 1.05; G = 1.27; G = 1.5; G = 2.167; and G = 3.19. In Figs. 15(a) and 15(b), the ST state in qZSI and AqZSI with improved PWM scheme is not applied, while the additional S0 switch in BC-VSI and AqZSI with improved PWM scheme is turned off. The efficiency of AqZSI with improved PWM scheme is slightly lower than that of BC-VSI and qZSI. This is because AqZSI uses more components than BC-VSI and qZSI. When the voltage gain is increased, the efficiency of BC-VSI is highest. In Fig. 15(c), the efficiency of AqZSI is slightly higher than qZSI when G = 1.27. However, the efficiency of AqZSI is always higher than that of qZSI when the voltage gain is higher than 1.27, as shown in Figs. 16(a)-16(c). According to the compared efficiency results, AqZSI with the improved PWM algorithm has a lower ST time and a lower voltage stress of H-bridge switches for the same voltage gain condition. Consequently, AqZSI has a much lower conduction loss in the H-bridge switches and diodes in boost mode when compared with qZSI. Moreover, a large ST duty cycle should be used in qZSI for high voltage gain requirement. This leads to increase in the conduction loss of the H-bridge circuit in qZSI. Therefore, qZSI is not suitable for high voltage gains.

Conclusion
An improved PWM control scheme for AqZSI was presented in this paper. Moreover, the optimal operation control of M, D, and D0 for AqZSI was derived to improve the efficiency and the modulation index. The comparative results between the three-phase BC-VSI, qZSI, and AqZSI under the optimal control condition showed that in boost voltage mode AqZSI with improved PWM scheme performs with a higher efficiency than qZSI but slightly lower than BC-VSI. However, the inductor current ripple of AqZSI with improved PWM scheme is lower than that of BC-VSI and qZSI when G is in the range of (2.56, 9.13] for BC-VSI and full range of G for qZSI. Moreover, AqZSI with proposed PWM scheme improves the modulation index and does not need the dead-time. Compared to conventional PWM scheme in [21] for AqZSI, the improved PWM scheme has higher modulation, lower voltage stress on capacitor C2, diode D1, and H-bridge switches, lower current stress of inductor L2 and shoot-through current stresses lead to reduce the inverter's size and power losses. The experimental results were presented to confirm the correctness of the analysis. It should be considered that AqZSI with improved PWM scheme can be used to replace qZSI for renewable energy system applications when a wide range of input voltage is required.

Acknowledgment
This research was supported by Korea Electric Power Corporation (Grant number: R18XA04).